Transnational power transmission and international law

تلعب شبكات نقل الطاقة دوراً بالغ الأهمية، وتحتاج كل دولة إلى وسائل لنقل الطاقة وتوصيلها، سواء كانت هذه الطاقة منتجة محلياً أو في بلدان أجنبية. يتناول البحث شبكات نقل الطاقة العابرة للحدود، والتي تهدف إلى توصيل الطاقة عبر الحدود الوطنية. ويلقي الضوء على التحديات التي تفرضها مسألة مراعاة الخصائص المميزة لشبكات الطاقة في المجالين القانوني والتنظيمي، وذلك بهدف تعزيز ترابط الشبكات عبر الحدود وانتقال الطاقة دون قيود بموجب القانون الدولي. وعلى الرغم من أن سياسة الطاقة التي وضعها الاتحاد الأوروبي لعام 2020 ونظام النقل الأوروبي لم ينجحا بعد في إنشاء سوق كهربي موحد، إلا أنهما يفيدان كدراسة حالة لنموذج محسّن من اللوائح التنظيمية التي تضع في اعتبارها إمكانية تنفيذ تداول الطاقة ونقلها عبر الحدود الوطنية. يطرح البحث رؤية تستند على أنه عند وضع نطاق عمل واختصاصات محددة بدقة وعلى أسس فنية لتفاعلات الشبكات الكهربية ونقل الطاقة عبر الحدود الوطنية، على المستوى الإقليمي، وإدراجها ضمن أنظمة تجارية دولية قائمة – مثل منظمة التجارة العالمية (WTO) أو معاهدة ميثاق الطاقة (Energy Charter Treaty ) المعدلة، فإن ذلك من شأنه أن يعزز تبادل الطاقة الدولي والتزامن بين منظومات الطاقة كعوامل محركة للقانون الدولي، مما يوفر قدر أكبر من المشروعية ويسهم في إمكانية تفعيل القانونPower transmission networks are crucial. Every country requires the means to transport and deliver energy, whether produced locally or in foreign countries. The paper deals with transnational power-transmission networks, those aimed at delivering energy across borders. It considers the challenges posed by transposing to the legal and regulatory fields the unique features of power grids in order to foster transnational network interconnections and unrestrained power transit under international law. The European Union 2020 Energy Policy and the European Transmission System, though still unsuccessful in achieving the creation of a single electricity market, serve as a case study for an enhanced model of regulation, with emphasis on the enforceability of power trading and transit across national borders. The research advances that a well-framed, technically-based, dedicated scope for transnational power grid interconnections and energy transit, at regional level, into ongoing international trading schemes such as the WTO or an improved Energy Charter Treaty, would further international power trading and synchronisation of energy matrices as drivers for international law to achieve greater legitimacy and enforceability

Hardware support for Local Memory Transactions on GPU Architectures

Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT execution model is not efficient when code includes critical sections to protect the access to data shared by the running threads. In addition, GPUs offer two shared spaces to the threads, local memory and global memory. Typical solutions to thread synchronization include the use of atomics to implement locks, the serialization of the execution of the critical section, or delegating the execution of the critical section to the host CPU, leading to suboptimal performance. In the multi-core CPU world, transactional memory (TM) was proposed as an alternative to locks to coordinate concurrent threads. Some solutions for GPUs started to appear in the literature. In contrast to these earlier proposals, our approach is to design hardware support for TM in two levels. The first level is a fast and lightweight solution for coordinating threads that share the local memory, while the second level coordinates threads through the global memory. In this paper we present GPU-LocalTM as a hardware TM (HTM) support for the first level. GPU-LocalTM offers simple conflict detection and version management mechanisms that minimize the hardware resources required for its implementation. For the workloads studied, GPU-LocalTM provides between 1.25-80X speedup over serialized critical sections, while the overhead introduced by transaction management is lower than 20%.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Improvements in Hardware Transactional Memory for GPU Architectures

In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Towards a Software Transactional Memory for heterogeneous CPU-GPU processors

The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip. Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes. However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism. Transactional Memory (TM) is an optimistic approach to implement mutual exclusion. With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses. TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors. In this paper we present APUTM, a software TM designed to work on heterogeneous APU processors. The design of APUTM focuses on minimizing the access to shared metadata in order to reduce the communication overhead via expensive platform atomics. The main objective of APUTM is to help us understand the tradeoffs of implementing a sofware TM on an heterogeneous CPU-GPU platform and to identify the key aspects to be considered in each device. In our experiments, we compare the adaptability of APUTM to execute in one of the devices (CPU or GPU) or in both of them simultaneously. These experiments show that APUTM is able to outperform sequential execution of the applications.This work has been supported by projects TIN2013-42253-P and TIN2016-80920-R, from the Spanish Government, P11-TIC8144 and P12- TIC1470, from Junta de Andalucía, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Pipeline template for streaming applications on heterogeneous chips

We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, we mainly focus on the API that allows the user to specify the type of parallelism exploited by each pipeline stage running on the multicore CPU, the mapping of the pipeline stages to the devices (GPU or CPU), and the number of active threads. We use a real streaming application as a case of study to illustrate the experimental results that can be obtained with this API. With this example, we evaluate how the different parameter values affect the performance and energy efficiency of a heterogenous on-chip processor (Exynos 5 Octa) that has three different computational cores: a GPU, an ARM Cortex-A15 quad-core, and an ARM Cortex-A7 quad-core.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. Proyecto de Excelencia de la Junta de Andalucía P11-TIC-08144

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Time Series Heterogeneous Co-execution on CPU+GPU

Time series motif (similarities) and discords discovery is one of the most important and challenging problems nowadays for time series analytics. We use an algorithm called “scrimp” that excels in collecting the relevant information of time series by reducing the computational complexity of the searching. Starting from the sequential algorithm we develop parallel alternatives based on a variety of scheduling policies that target different computing devices in a system that integrates a CPU multicore and an embedded GPU. These policies are named Dynamic -using Intel TBB- and Static -using C++11 threads- when targeting the CPU, and they are compared to a heterogeneous adaptive approach named LogFit -using Intel TBB and OpenCL- when targeting the co-execution on the CPU and GPU.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech